创建Vivado工程
- 1.创建工程:
在Vivado中创建工程,命名随意,路径随意;
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234711796-937942639.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234720404-163804118.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234727170-693476122.png)
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234733654-1496510250.png)
- 2.配置工程:
这里可以选择是否添加源文件等,我们先不添加;
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234740603-346225792.png)
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234747219-417626066.png)
- 3.选择FPGA核心:
选择MCU200T对应的FPGA核心xc7a200tfbg484-2
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412224443545-580295751.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412224531439-557025195.png)
等待创建中~
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234809333-2014111913.png)
- 4.添加源文件:
创建工程完成后,单击"+",添加源文件,这里我们选择添加的是文件夹e203(路径为e203_hbirdv2/rtl/e203),Finish完成添加,那两个勾建议可以勾选,会将添加的源文件拷贝到我们的工程目录下,防止对原始文件造成改动;
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234815198-1964965193.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234937353-835813600.png)
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234943122-2144294045.png)
- 5.添加头文件:
同上操作,找到MCU对应的system.v文件(路径为e203_hbirdv2-master\fpga\mcu200t\system.v);
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234952690-557216938.png)
- 6.设置头文件:
添加完成后,右键点击system.v将其设置为头文件;
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307234959368-836535567.png)
- 7.调用IP核:
这时,我们会观察到有两个文件有问题,这是由于e203中调用了相应的IP核,我们也要在工程中对应添加;
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235030581-131525557.png)
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235037232-1673582209.png)
- 8.添加reset_sys:
在IP目录中找到对应IP核Processor System Reset,双击将名字改为system.v中的对应名字reset_sys。注意!这里一定要保持名称一致!后修改其复位的优先级为最高,即可完成IP核的调用;
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235043473-214265157.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235049943-2027512922.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235056084-1708656437.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235104695-349855779.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235213517-1145462764.png)
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235221954-2116564802.png)
- 9.添加clk:
在IP目录中找到对应IP核Clocking Wizard,同上操作,将名改为mmcm,修改生成时钟频率为16M,改变复位方式为低电平复位,即可完成IP核的调用;同时应注意这里IP核调用的例化名称应与system.v中保持一致。
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235228960-1573130725.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235235833-2010814274.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235243033-1853803142.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235249837-111525553.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235257531-118217682.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235304556-1441523754.png)
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235310936-1989396206.png)
- 10.修改顶层定义文件:
右键单击e203_defines.v,将其设为global define,并在其文件头添加语句:`define FPGA_SOURCE。完成后查看Elaborated Design,若此时报错无法打开e203_defines.v文件,可以在SourceFileProperties中将其对应文件类型改为Verilog Header
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235343274-1960777731.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235350140-567419265.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235358200-950330301.png)
![](https://img2023.cnblogs.com/blog/2326690/202303/2326690-20230307235407162-1880374199.png)
NucleiStudio创建工程
- 1.安装NucleiStudio:
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230411180455415-1783286885.png)
- 2.配置JDK:
下载完成后,直接解压NucleiStudio压缩包,双击exe文件即可运行。如果没有成功打开,可参考以下过程进行JDK的配置:
NucleiStudio将JRE、Eclipse、GNU MCU Eclipse 插件、RISCV-V 交叉工具链、Windows Build Tools打包在了一起。所以NucleiStudio 本质上还是Eclipse,而是基于Java开发的,所以需要Java的软件开发工具包——JDK。
双击jdk-8u152-windows-x64.exe,选择安装目录,然后下一步
完成后,单击"计算机-属性-高级系统设置",单击"环境变量",新建:变量名为:JAVA_HOME,变量值为安装目录下的jdk文件夹
配置PATH,变量名:Path,变量值:%JAVA_HOME%\bin
新建CLASSPATH,变量名:CLASSPATH,变量值:.;%JAVA_HOME%\lib\dt.jar;%JAVA_HOME%\lib\tools.jar
测试是否安装成功:window+R打开cmd窗口,输入javac出现如下说明配置成功
- 3.启动NucleiStudio
启动后,会让选择workstation,找一块自己满意的地方放就行。
按照以下步骤新建Helloworld例程????
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412224737152-1680990398.png)
![Nucleistudio+Vivado协同仿真教程-小白菜博客](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412224806445-1859070546.png)
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412224853139-1817200793.png)
因为前面建立工程时我们选择的是ILM启动,即从内部ROM启动,故需要修改 .cfg 配置文件,位置如下????
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412225023109-1686976996.png)
双击打开后,将划线的flash启动部分注释掉
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412225210011-1923906440.png)
然后修改Build选项,使反汇编生成机器指令文件:右键工程,点击properties
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412225321823-2029811815.png)
在C/C++ Build/Setting中添加如下指令:
riscv-nuclei-elf-objcopy -O verilog "${BuildArtifactFileBaseName}.elf" "${BuildArtifactFileBaseName}.verilog";sed -i 's/@800/@000/g' "${BuildArtifactFileBaseName}.verilog"; sed -i 's/@00002FB8/@00002000/g' "${BuildArtifactFileBaseName}.verilog";
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412225451075-292283480.png)
最后点击锤子????即可编译整个工程
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412225636769-481936029.png)
编译完成后,我们会在工程目录下发现生成了.verilog文件,此即为我们仿真需用到的文件,可以将改文件复制保存在tb目录下
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412225747479-1996793656.png)
联合仿真
在我们前面创建的Vivado工程中添加仿真文件(e203_hbirdv2-master\e203_hbirdv2-master\tb\tb_top.v),然后修改我们要验证的仿真文件对应路径,
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412225937619-587993583.png)
最后在Vivado中进行行为级仿真即可得到我们想要验证的结果
![](https://img2023.cnblogs.com/blog/2326690/202304/2326690-20230412231211015-698803193.png)